The inventions relate to semiconductor memory devices, and more particularly, to a semiconductor memory device that requires a refresh operation and that includes a redundancy memory cell.
A semiconductor memory device such as a dynamic random access memory (DRAM) may be considered to be an inferior product when just one memory cell in the device is defective. However, it is inefficient to discard all the memory devices that have one or more defective memory cells in terms of the yield (the percentage of devices obtained from a wafer that perform acceptably). To address this problem, redundancy memory cells are often included in a semiconductor memory device, and a defective memory cell can be replaced with one of the redundancy memory cells, thereby improving the yield.
Not all memory cells in a device such as a DRAM have identical operating characteristics. Some memory cells can be considered weak because they may, especially under some operating conditions, require more frequent refreshing than non-weak cells to ensure proper data retention.
A semiconductor memory device may perform a refresh leveraging operation to improve the data retention characteristics of weak memory cells. When the refresh leveraging operation is applied to the semiconductor memory device, the weak memory cells may be refreshed more frequently than other memory cells.
However, because generally in a memory system with redundancy cells the refresh leveraging operation is limited to weak memory cells among non-redundancy memory cells (sometimes referred to as the “normal” or “primary” memory cells), there is a need to develop designs and methods of improving not only the performance of the normal or primary memory cells but also the performance of the redundancy memory cells in order to maximize the yield.